As is well known, a solid state drive (hereinafter, SSD) is a data storage drive that uses NAND flash memories to store data. Solid state drive with NAND flash memories is a non-volatile memory device. After being written to the non-volatile memory, the data are retained in the solid state drive even if power supply system is off.
Each memory cell in the flash memories comprises a single transistor with an additional floating gate called floating gate transistor. During programming cycle, hot carriers are injected to the floating gate transistor. According to the amount of hot carriers being injected to the floating gate, threshold voltage of the floating gate transistor changes, so as storage status of the memory cell. During erasing cycle, hot carriers are ejected from the floating gate transistor.
Flash memories can be classified according to internal design of their memory cells. For instance, a flash memory may be a single-level cell (hereinafter, SLC), or multi-level cell (hereinafter, MLC) such as double-level cell, triple-level cell, quadruple-level cell etc.
SLC flash memory is expensive but with faster performance and greater reliability. SLC flash memory can be erased for dozens of thousand times, but SLC flash memory stores only one bit value per cell. Relatively, a triple-level cell flash memory is with slow performance but cost less. Erasing endurance of the triple-level cell flash memory is less than a thousand times, and the triple-level cell flash memory stores 3 bits value per cell. Performance, cost, and endurance characteristics of the double-level cell flash memory are in-between of those of the SLC flash memory and the triple-level cell flash memory. Erasing endurance of the double-level cell flash memory is between 1000 to 5000 times, and the double-level cell flash memory stores 2 bits value per cell.
In other words, storage density of triple-level cell flash memory is relatively higher, and that of the SLC flash memory is relatively is lower.
FIG. 1 is a schematic diagram illustrating relations between the threshold voltage distributions and storage states of various flash memories. The SLC flash memory stores one bit of data per cell (1 bit/cell). Hence, according to the amount of hot carriers being injected, two distinct distributions of threshold voltage may be generated at the floating gate transistor in memory cell of SLC flash memory. Each distribution of the threshold voltage represents a storage state. For instance, assuming that a memory cell is at a storage state “state-0” when the memory cell is with low threshold voltage, and at a storage state “state-1” when the memory cell is with high threshold voltage. The storage states “state-0” and “state-1” represent two different storage states. In some cases, a first storage state and a second storage state may be used to represent two distinct distributions of threshold voltage.
Similarly, the double-level cell flash memory stores 2-bits of data per cell (2 bits/cell). Hence, according to the amount of hot carriers being injected, four distinct distributions of the threshold voltage may be generated at the floating gate transistor in memory cell of the double-level cell flash memory. These four distributions are used for representing four different storage states. For example, assuming that voltage levels of threshold voltages ranging from low to high are corresponding to the following storage states, “state-00”, “state-01”, “state-10”, and “state-11”, respectively.
The triple-level cell flash memory stores 3-bits of data per cell (3 bits/cell). According to the amount of hot carriers being injected, eight distinct distributions of the threshold voltage may be generated at the floating gate transistor in memory cell of the triple-level cell flash memory. These eight distributions are used for representing eight different storage states. For example, assuming that voltage levels of threshold voltages ranging from low to high are corresponding to the following storage states, “state-000”, “state-001”, “state-010”, “state-011”, “state-100”, “state-101”, “state-110”, and “state-111”, respectively.
The quadruple-level cell flash memory stores 4-bits of data per cell (4 bits/cell). According to the amount of hot carriers being injected, sixteen distinct distributions of the threshold voltage may be generated at the floating gate transistor in memory cell of the quadruple-level cell flash memory. These sixteen distributions are used for representing sixteen different storage states. For example, assuming that voltage levels of threshold voltages ranging from low to high are corresponding to the following storage states, “state-0000”, “state-0001”, “state-0010”, “state-0011”, “state-0100”, “state-0101”, “state-0110”, “state-0111”, “state-1000”, “state-1001”, “state-1010”, “state-1011”, “state-1100”, “state-1101”, “state-1110”, and “state-1111”, respectively.
Based on the above illustrations, during programming cycle, storage state and threshold voltage of the flash memory cell will change when the amount of hot carriers being injected changes. SLC flash memory requires only one programming procedure for changing to the demand storage state. However, in order to change to a demand storage state, multiple programming procedures are required for the MLC flash memories.
Details of the triple-level cell flash memory will be illustrated for example. FIG. 2A is a schematic diagram illustrating control flow of programming the triple-level cell flash memory to the storage state “state-100”. It is assumed that three programming procedures are required for programming the triple-level cell flash memory to the storage state “state-100”.
During the first programming procedure, a first program voltage is provided, for changing the storage state of the memory cell to the storage state “state-111”. Consequently, during the second programming procedure, a second program voltage is provided, for changing the storage state of the memory cell to the storage state “state-101”. At the end, during the third procedure, a third program voltage is provided, for changing the storage state of the memory cell to the storage state “state-100”.
That is, a final storage state is required to be known in advance, then the three programming procedures can be determined. Dotted lines in FIG. 2A are used for illustrating how to program the triple-level cell flash memory to the storage state “state-011”. A complete programming procedure includes a first programming procedure of changing the storage state of the memory cell to the storage state “state-000”, a second programming procedure of changing the storage state of the memory cell to the storage state “state-010”, and a third programming procedure of changing the storage state of the memory cell to the storage state “state-011”. Details of programming procedure regarding how to control the triple-level memory cell to change to other storage states are similar to the ones in FIG. 2A, and are not redundantly described herein.
According to the illustrations above, the memory cell of the triple-level cell flash memory can be programmed to only two distinct storage states after the first programming procedure, four distinct storage states after the second programming procedure, and eight distinct storage states after the third programming procedure. In other words, three programming procedures are required for achieving eight distinct storage states of the triple-level cell flash memory.
As shown in FIG. 2B, two programming procedures are required for achieving four distinct storage states of the double-level cell flash memory. Similarly, four programming procedures are required for the quadruple-level cell flash memory.
Moreover, programming duration for each programming procedure of the MLC flash memory may vary, and the triple-level cell flash memory is illustrated as an example. The first programming procedure of the triple-level cell flash memory costs about 1 ms, the second programming procedure costs more than 2.5 ms, and the third programming procedure costs about 7.0 ms. Basically, the first programming procedure is the shortest, and the third programming procedure is the longest.
In short, the more voltage levels exist in the MLC flash memory, the more programming procedures are required to change the storage state of the MLC flash memory. Besides, the whole programming duration will be longer. Furthermore, duration of the first programming procedure is the shortest while duration of the last programming procedure is the longest.
FIG. 3 is a schematic diagram illustrating a conventional solid state drive. The solid state drive 300 includes a control unit 301, a buffer unit 307, and a flash memory 305. The control unit 301 is electrically connected to the buffer unit 307 and the flash memory 305. Moreover, an external bus 310 is used for transmitting data between the control unit 301 and the host 320. Basically, when the host 320 issues data-for-writing to the flash memory 305, the control unit 301 first starts to proceed an ECC encoding procedure. After the ECC encoding procedure, the data-for-writing are transformed to data-for-storage, which are temporarily stored in the buffer unit 307. Afterwards, the control unit 301 records data-for-storage to the flash memory 305 timely. The buffer unit 307 may be an SRAM or a DRAM. That is, data-for-storage stored in the buffer unit 307 will be lost if the solid state drive 300 encounters power failure. The external bus 310 may be a USB bus, an IEEE 1394 bus, a SATA bus, or the like. The flash memory 305 may be a SLC flash memory, or a MLC flash memory.
It is known that, the control unit 301 of the solid state drive 300 stores data to the flash memory 305 in units of page. Size of each page is defined by the manufacturer of the flash memory 305. For instance, each page may be composed of 2K bytes of data, 4K bytes of data, or 8K bytes of data. The flash memory with size of 4K-byte page is illustrated as an example. Assuming that size of the data-for-storage is 4224 bytes, and the data-for-storage includes user data, encoding data, and other related data. In such case, 4224×8 memory cells are required for programming all the data-for-storage by a SLC flash memory.
Comparing to the SLC flash memory, MLC flash memories are with higher storage densities. Hence, the double-level cell flash memory with 4224×8 memory cells is capable of storing two pages of data. Similarly, the triple-level cell flash memory with 4224×8 memory cells is capable of storing three pages of data. The quadruple-level cell flash memory with 4224×8 cells is capable of storing four pages of data.
FIGS. 4A and 4B are schematic diagrams illustrating that two pages are used for storing data to the double-level cell flash memory. The first byte (Byte-1) is illustrated as an example. Assuming that data stored at the first byte in page M is 0x65h (01100101b), and data stored at the first byte in page N is 0xDBh (11011011b). As shown in FIG. 4A, during the first programming procedure, data of the first bye in page M (01100101b) is programmed to the 8 memory cells of the double-level cell flash memory. Afterwards, the storage states of the 8 memory cells are changed to “state-00”, “state-11”, “state-11”, “state-00”, “state-00”, “state-11”, “state-00”, and “state-11”, respectively.
According to FIG. 4B, after the second programming procedure, data of the first byte in page N (11011011b) is programmed to the 8 memory cells of the double-level cell flash memory. Afterwards, the storage states of the 8 memory cells are changed to “state-01”, “state-11”, “state-10”, “state-01”, “state-01”, “state-10”, “state-01”, and “state-11”, respectively.
Based on above illustrations, the double-level cell flash memory with 4224×8 memory cells stores only data of the first byte in page M. Moreover, for the double-level cell flash memory with 4224×8 memory cells, a second programming procedure is required for storing data of both the first bytes of the page M and the page N.
According to specification of the MLC flash memories, pages being programmed during the first programming procedure are defined as strong-page. Pages being programmed during the second programming procedure are defined as weak-page. Alternatively speaking, programming procedure for strong-page is required to be executed prior to that of the weak-pages. For instance, programming two pages of data costs 3.5 ms (1 ms+2.5 ms) for the double-level cell with 4244×8 memory cells.
FIG. 5 is a flow diagram illustrating conventional programming procedures for the solid state drive composed of multi-level cell flash memories. After the solid state drive is powered on, the solid state drive receives data-for-writing (writing data) from the host and transforms the data-for-writing to data-for-storage (step S502). Consequently, the solid state drive proceeds a strong-page programming procedure to a blank area of the flash memory (step S504). The strong-page programming procedure is followed by a weak-page programming procedure (step S506). After all programming procedures (step S504 and step S506) are completed, the whole programming operation is done. The solid state drive again executes the step of receiving data-for-writing from the host (step S502), for proceeding programming procedures of other pages. The blank area of the flash memory may be a region without any data, or an erased region.
Moreover, number of the programming procedures for weak-page (S506) is determined by types of the MLC flash memory. For the double-level cell flash memory, only one weak-page programming procedure is required before the step S502 is executed again. For the triple-level cell flash memory, two weak-page programming procedures are required before the step S502 is executed again. For the quadruple-level cell flash memory, three weak-page programming procedures are required before the step S502 is executed again.
According to the control flow shown in FIG. 5, when the power remains on, the control unit of the solid state drive programs data to the MLC flash memory in pages. However, when the solid state drive encounters an unexpected power-failure, the above control flow for programming data takes too much time and may be interrupted. Consequently, the programming procedure may fail, and the programmed data may be incorrect or missing.